1. Technical Field
The present disclosure relates to a semiconductor memory device, more particularly, to a non-volatile memory device having a dual gate and a method of forming the same.
2. Disclosure of Related Art
Semiconductor memory devices may be classified into volatile memory devices and non-volatile memory devices. A volatile memory device loses stored data when power to the device is cut off. DRAM devices and SRAM devices are examples of volatile memory devices. A non-volatile memory device maintains stored data even when power to the device is cut off. A flash memory device is an example of a non-volatile memory device.
In a conventional flash memory cell, electric charges in the form of free carriers are stored within an isolated floating gate. Silicon-Oxide-Silicon (SONOS) memory devices, which store electric charges within a deep level trap, have also been investigated.
SONOS memory devices are non-volatile memory devices. A flash memory cell may lose all electric charges if a part of a tunnel oxide suffers from defects because electric charges are stored in the form of free carriers. To the contrary, a SONOS memory device maintains electric charges even if a part of the tunnel oxide suffers from defects because electric charges are stored in an isolated deep level trap. Accordingly, the tunnel oxide of SONOS memory devices can be formed thinner than that of flash memory devices having a floating gate. Consequently, it is possible for SONOS memory devices to operate with low voltage as compared with flash memory devices having a floating gate. There are two conventional methods of storing data in SONOS memory devices. These methods are the Fowler-Nordheim tunneling (FN tunneling) method and the hot carrier injection method.
A SONOS memory cell is disclosed in U.S. Pat. No. 5,768,192 entitled Non-volatile Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping, issued to Eitan et al. A program operation for a conventional SONOS memory cell is explained below with reference to FIG. 1.
Referring to FIG. 1, a first silicon oxide layer ‘2’, a silicon nitride layer ‘3’, a second silicon oxide layer ‘4’ and a gate electrode ‘5’ are sequentially stacked on a semiconductor substrate ‘1’. Source region ‘6’ is formed at one side of the gate electrode ‘5’ and drain region ‘6a’ is formed at another side of the gate electrode ‘5’ in the semiconductor substrate ‘1’.
According to the operation of the SONOS memory cell having the above structure, programming voltage is applied to the gate electrode ‘5’ and drain voltage is applied to the drain region ‘6a’. Ground voltage is applied to the source region ‘6’. Accordingly, hot carrier injection occurs at portions neighboring the drain region ‘6a’. Consequently, electronic charges are stored at a predetermined region of the silicon nitride layer ‘3’, so that charging region ‘k’ is formed. The charging region ‘k’ is adjacent to the drain region ‘6a’.
In the conventional SONOS memory cell, the distance between the source region ‘6’ and drain region ‘6a’ may be shortened to accommodate high integration of a semiconductor device. Accordingly, punch through between drain/source regions ‘6’ and ‘6a’ may take place during program operation. Thus, SONOS memory cells have not been widely used because of their inability to be highly integrated.